The 2nd Workshop on "MOA: Measuring and Optimizing Heterogeneous AI Architectures"
The 2nd Workshop on "MOA: Measuring and Optimizing Heterogeneous AI Architectures"
Chair: Prof. Hyuk-Jae Lee, Seoul National University
Co-chair: Prof. Soojung Ryu, Seoul National University / Xenoscube Inc.
Co-chair: Joohoon Lee, Senior Director / Nvidia
Jeehoon Kang, Chief Research Officer / FuriosaAI
Jongsok Choi, Engineering Manager / META
Jun-Seok Park, Professor / Seoul National University
MOA focuses on heterogeneous AI architectures, benchmarking, and optimization methodologies. The previous workshop featured:
Academia and industry invited talks
AI benchmarking and optimization sessions
Edge AI optimization competition using DeepX M1 SoC
Participants included researchers from academia, AI semiconductor companies, and AI systems communities.
The rapid growth of AI models-from foundation models in datacenters to resource-constrained edge AI-creates system-level challenges requiring efficient heterogeneous computing architectures.
MOA provides a workshop to discuss architectural innovations and hardware-software co-design strategies spanning CPU-GPU-NPU servers, accelerators, and edge AI systems as well.
The workshop combines technical discussions with a practical benchmarking competition on production AI accelerator platforms, enabling participants to explore real-world optimization challenges involving modern AI workloads. MOA aims to bridge computer architecture, systems, compiler/runtime, and AI infrastructure communities. Beyond discussion, MOA emphasizes practical insight through benchmarking and optimization exercises, allowing participants to quantify optimization strategies on real hardware platforms.
Topics include but are not limited to:
Heterogeneous AI architectures
Hardware-software co-design
AI benchmarking methodologies
Cloud and edge inference optimization
Compiler/runtime optimization
Memory-centric AI infrastructure
Emerging AI workloads (LLMs, diffusion, SSMs, agentic AI)
MOA aims to:
Strengthen collaboration across AI systems communities
Disseminate practical optimization methodologies
Encourage research in NPU software ecosystems
Advance benchmarking and heterogeneous AI infrastructure research
Hyuk-Jae Lee is a Professor in the Department of Electrical and Computer Engineering at Seoul National University. His primary research interests lie in computer architecture and parallel processing systems, with a strong focus on hardware accelerators for AI and next-generation memory systems. His recent work delves into memory-centric computing platforms using Processing-in-Memory (PIM) and CXL (Compute Express Link), data compression techniques for deep learning acceleration, and the design of high-performance AI semiconductors.
Before joining SNU, he was a Senior Engineer at Intel Corporation. He also has extensive leadership experience, having served as the Chair of the ECE Department at SNU (2019-2023). His deep expertise spanning industry and academia in both computer architecture and AI systems makes him exceptionally well-suited to lead this workshop. He received his Ph.D. in Electrical and Computer Engineering from Purdue University.
Soojung Ryu is a Visiting Professor at Seoul National University and CEO of Xenoscube Inc., specializing in AI systems, heterogeneous computing, and advanced AI infrastructure. She previously served as the founding CEO of SAPEON, leading the AI semiconductor company following its spin-off from SK Telecom. Her research and industry activities focus on AI accelerators, benchmarking methodologies, and software-hardware co-design for next-generation AI systems.
Prior to her role at SAPEON, her career was marked by over a decade of leadership at Samsung Electronics, where she served as a Vice President and spearheaded the development of mobile GPUs and the Samsung Reconfigurable Processor (SRP).
Dr. Jeehoon Kang is the Chief Research Officer (CRO) at FuriosaAI. Before joining the industry, he was an Associate Professor of Computer Science at KAIST after receiving his Ph.D. under the supervision of Prof. Chung-Kil Hur at Seoul National University. As a specialist in concurrency, compilers, and software verification, he has published over 30 papers in premier venues such as MICRO, ASPLOS, SOSP, and PLDI.
At FuriosaAI, Dr. Kang applies his academic expertise in computer systems to solve engineering challenges in industrial-scale deployment. He leads the development of kernel programming models to maximize the performance of the RNGD accelerator, alongside building the application software stack for reinforcement learning and agentic AI.
Joohoon Lee is a Senior Director of Product for AI Platform Software at NVIDIA. He leads the AI Platform Software team, which develops and advances industry-leading training frameworks such as PyTorch, JAX, and Megatron Core, as well as inference solutions including TensorRT-LLM and Model Optimizer. His organization also delivers high-performance kernels and communication libraries, including cuDNN, CUTLASS, NCCL, and NIXL, enabling scalable and efficient AI workloads across a wide range of applications.
Jongsok Choi is an Engineering Manager at Meta, leading the teams building TorchInductor, PyTorch's compiler stack for performance optimizations, and Helion, a Python-embedded domain-specific language designed to make machine learning kernel authoring easier, performant, and portable across heterogeneous hardware.
Jongsok earned his Ph.D. in Computer Engineering from University of Toronto and has more than 15 years of experience in compilers, high-level synthesis and hardware acceleration. He co-founded LegUp Computing, a startup commercializing his doctoral research on compiler technologies to automatically accelerate software to hardware. Following the company's acquisition by Microchip Technology, Jongsok served as the Microchip Toronto site director. Across academia and industry, Jongsok has co-authored 17 journal and conference publications and is the inventor of 7 U.S. patents.
Jun-Seok Park received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2009, 2011, and 2015, respectively. He is currently an Assistant Professor with Seoul National University. From 2015 to 2026, he was a Lead Hardware Architect and Design Engineer with the System LSI Division, Samsung Electronics, Hwaseong, South Korea, where he contributed to the development of ten generations of Samsung's NPU as a lead HW architect. His research interests include high-performance, low-power NPU architectures and memory hierarchy design for large-scale ML systems.